This invention relates to a digital clock throttling means, and more specifically to a digital clock throttling means employed in a graphics chip for responsive to an input value to gate a clock signal (CLK) of the graphics chip.
With the improvement of the VLSI fabricating technology and the raising demand of performance, an integrated circuit has become more compact and complicated than ever. For example, a layout of graphics chip becomes more complicated, due to the requirement of three-dimensional graphics. Although the highly integrated chips provide strong calculating performance, they may cause some undesired issues. One of the most important issues is the high power consumption, due to the high integration of the chips. Usually, the high power consumption accompanies a thermal-raising problem. For some portable devices, such as laptop computers and personal digital assistants, the thermal-raising problem would get even worse, because of their limited spaces, which restrict the implantation of cooling means, unable to transfer heat out of them. Therefore, it sometimes sees that the chips, in the portable devices burn out for lack of a suitable temperature control scheme.
One of the conventional methods of reducing the power consumption in an integrated circuit is to turn off some functions inherent in the integrated circuit by software or hardware. Since some functions of the integrated circuit have been suspended, it would be performed under a less-loaded state, thereby reducing its total thermal production. Although the conventional method reduces the thermal production by suspending some functions of the integrated circuit, it causes some serious disadvantages. For example, in a graphics chip, if some functions were suspended, the pictures on the display would be interrupted. When the graphics chip is employed to support a computer game, the pictures of the game would be displayed discontinuously, due to the suspension of some functions. Therefore, the conventional method may avoid the high temperature problem of the integrated circuit, but might degrade the performance of the integrated circuit.
Another conventional method employs a phase-locked loop (PLL) circuit to change the clock speed of the integrated circuit, i.e. clock throttling. However, the latency of using phase-locked loop circuit to reduce the clock speed and bring it back is large. Thus, it""s also unacceptable to be implanted in some integrated circuits requiring high performance, such as graphics chips.
An objective of this invention is to provide a digital clock throttling means for adjusting a frequency of clock signal of an integrated circuit.
Another objective of this invention is to provide a temperature controlling apparatus employing the digital clock throttling means for adjusting a frequency of clock signal of an integrated circuit in response to its temperature.
Yet another objective of this invention is to provide a power controlling apparatus employing the digital clock throttling means for adjusting a frequency of clock signal of an integrated circuit in response to its loading.
This invention discloses a digital throttling means including an accumulator and gating circuit. The accumulator responses to an input throttling value to generate a throttling signal. The gating circuit responses to the throttling signal to gate out some clock cycles of an integrated circuit the digital clock throttling means implants in, therefore, changing the frequency of the clock signal as well as controlling the power consumption and thermal production. For better applications, the digital clock throttling means can be implanted in a temperature controlling apparatus and power controlling apparatus embedded in any integrated circuits, such as graphics chips.